Managing power consumption is an important aspect of designing electronic devices. Minimizing the power consumed by individual components within an electronic device results in less heating and a lower draw on the device power supply. This can result in more satisfactory performance, a longer operational lifetime and, in the case of portable devices, longer battery life.
Leakage currents in integrated circuits provide an undesirable drain on an electronic device's power supply. Managing low level leakage currents is an effective step in minimizing unwanted power consumption in electronic devices. One method for managing low level leakage is to disconnect integrated circuits from the device power supply during periods of inactivity when the logical functions of the integrated circuit are not required. Often there are significant periods of time during the normal operation of electronic devices in which various components, including integrated circuit chips, are not in use. High level leakage can be completely eliminated from an integrated circuit chip during dormant periods by simply cutting the power supplied to the integrated circuit chip. Power may be restored to the integrated circuit chip when the operation of the device in which the chip is installed again requires the logical functions provided by the integrated circuit chip.
However, implementing a power management regimen that includes disconnecting the power to an integrated circuit chip during periods of dormancy, and reconnecting power in advance of active periods, raises a number of problems that must be addressed. For example, very large-scale integrated circuit chips often include multiple power connections in order to evenly distribute the current flowing into the logic circuits contained on the integrated circuit chip. A low leakage power management system must be capable of switching each power connection in a controlled manner to ensure that excessive in-rush currents are prevented on individual power connections. Care must also be taken when disconnecting the power supplied to the integrated circuit chip in order to prevent unpredictable intermediate voltages on the integrated circuit chip's internal supply voltage bus from generating false or otherwise improper output signals.